1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more particularly, to semiconductor integrated circuit devices including a plurality of dispersedly arranged cell array blocks.
2. Description of the Related Art
FIG. 7 is a diagram showing a layout on a conventional semiconductor memory chip. An input/output buffer region 7 is formed on the peripheral portion of a semiconductor chip 1 and a chip control circuit region 8 is formed on the central portion of semiconductor chip 1. Four memory cell array blocks 9 are formed on semiconductor chip 1.
Input/output buffer region 7 includes a bonding pad for inputting an externally applied signal and outputting a signal to the outside of the chip, a buffer for input/output signals including an address signal, some of peripheral circuits and signal interconnection therebetween.
A chip control circuit region 8 includes a control circuit for controlling each circuit in chip 1 and an address signal generation circuit such as a predecoder.
Each memory cell array block 9 includes a memory cell array having a capacity one-fourth of the storage capacity of the entire chip, a decoder, a sense amplifier, an input/output latch and some of control circuits for driving these circuits.
FIG. 8 is a functional block diagram showing the detailed arrangement of the semiconductor memory of FIG. 7. Chip 1 includes bonding pads (hereinafter referred to as pads) P1-P7, an input/output buffer circuit 70, a chip control circuit 80 and four memory cell array blocks 90. Pads P1-P7 and input/output buffer circuit 70 are formed in input/output buffer region 7 of FIG. 7. Chip control circuit 80 is formed in chip control circuit region 8 of FIG. 7. Each memory cell array block 90 corresponds to each memory cell array block 9 of FIG. 7.
Input/output buffer circuit 70 includes a data out buffer 801 in the final stage, and a data in buffer 802, address buffers 803 and 804, a row address strobe buffer 805, a column address strobe buffer 806 and a write enable buffer 807 all of which are in the first stage.
Data out buffer 801 outputs data Dout applied from chip control circuit 80 to pad P1. Data in buffer 801 inputs external data Din applied through pad P2 to chip control circuit 80. Address buffers 803 and 804 input external address signals A0-An applied through pads P3 and P4 to chip control circuit 80. Row address buffer 805, column address strobe buffer 806 and write enable buffer 807 input external row address strobe signal RAS, column address strobe signal CAS and write enable signal WE applied through pads P5, P6 and P7, respectively, to chip control circuit 80.
Chip control circuit 80 includes a data input/output buffer and selector 808, a block select circuit 809, an address buffer and predecoder 810 and a clock generator 811.
Clock-generator 811 controls data input/output buffer and selector 808, block select circuit 809 and address buffer and predecoder 810 in response to the row address strobe signal RAS, the column address strobe signal CAS and the write enable signal WE. Address buffer and predecoder 810 predecodes address signals A0-An and applies the predecoded signals to memory cell array blocks 90 and block select circuit 809. Block select circuit 809 selects one of the four memory cell array blocks 90 and activates the same. Data input/output buffer and selector 808 applies data read from the selected memory cell array block 90 to data out buffer 801 in a reading operation. Data input/output buffer and selector 808 also applies data applied from data in buffer 802 to the selected memory cell array block 90 in a writing operation.
Each memory cell array block 90 includes a memory cell array 901, a memory cell array block generator 902, a column decoder 903, a row decoder 904, an input/output latch 905 and a sense amplifier 906.
Memory cell array block clock generator 902 controls each circuit in memory cell array block 90. Column decoder 903 and row decoder 904 designate an address of a memory cell in memory cell array 901 in response to a predecoded signal. In a reading operation, data read from memory cell array 901 is amplified by sense amplifier 906 and applied to data input/output buffer and selector 808 through input/output latch 905. In a writing operation, the data applied from data input/output buffer and selector 808 is written in memory cell array 901 through input/output latch 905.
An operation of the semiconductor memory will be schematically described with reference to FIG. 7. Data, address signals and control signals input through the pads in input/output buffer region 7 are amplified by the input/output buffers in input/output buffer region 7 and transmitted to chip control circuit region 8 arranged at the center of chip 1. In chip control circuit region 8, an address signal selects one of the four memory cell array blocks 9. A writing or reading operation is performed in the selected memory cell array block 9.
In a reading operation, data read from the selected memory cell array block 9 is transmitted to chip control circuit region 8 at the center of chip 1 wherein the data is amplified. The amplified data is transmitted to input/output buffer region 7 and output to the outside of the chip through the output buffer and the pad.
Thus, a control signal or an address signal generated in chip control circuit region 8 arranged at the center of chip 1 drive memory cell array blocks 9 arranged externally to chip control circuit region 8. As a result, a length of the interconnection between chip control circuit region 8 and each memory cell array block 9 is approximately half the longer side of chip 1, causing signal delay due to the interconnection.
In order to prevent such signal delay, the size of a transistor for driving signals is increased, thereby enhancing current drivability.
The number of signals generated in chip control circuit region 8 is several times the number of signals input or output from or to the outside of the chip. Thus, circuits for generating a part of the signals for driving the memory cell array is located in each memory cell array block 9. As a result, the number of signals transmitted from chip control circuit region 8 to each memory cell array block 9 is reduced to decrease the load of the circuits for generating the signals for driving the memory cell array, thereby achieving a high-speed operation and reduction in power consumption.
However, chip control circuit region 8 arranged at the central portion of chip 1 increases a length of a signal interconnection between control circuits (by the amount approximately as long as the shorter side of chip 1).
As described above, the length of the signal interconnection between chip control circuit region 8 and each memory cell array block 9 is increased. In addition, a signal interconnection is increased in such a region including a large number of signal interconnections as chip control circuit region 8. Each load capacitance is also increased to increase signal delay due to the interconnections.
Enhancing current drivability of a signal generation circuit to reduce such delay results in an increase in a chip area and power consumption.